I’m plugging away at building an inexpensive, high-bandwidth software-defined radio receiver. I built a bunch of PLL+VCO boards, filter boards, and quadrature mixer boards. But I still don’t have a good ADC to sample the signals I’m receiving. No longer! I just submitted a four-layer design to Laen’s Dorkbot PDX PCB Order, which should give me 10 MHz of bandwidth:
A quick overview of the board’s design:
- SMA connectors for the baseband quadrature input signal. There are two differential inputs, so four connectors total.
- Two-channel high-speed ADC from Linear Technologies. I designed with the 16-bit, 125MHz LT2185 in mind, but Linear offers many pin-compatible devices that are cheaper, with the attendant trade-offs in sample rate and resolution.
- Sampling oscillator in a standard 7mm x 5mm footprint. I’m planning to use a low phase noise oscillator like the Connor-Winfield CWX813.
- Lattice XP2-5 FPGA for sample rate conversion.
- FTDI FT2232H high-speed USB interface.
- Configuration and FT2232H pin breakout so I can experiment with USB-based FPGA code updating.
- JTAG interface for initial development.
- Power input — approximately 3.7V minimum.
USB 2.0 high-speed performance is a bottleneck for software radio. On a good day, you can get 35 MBytes/second. Assuming 12-bit quadrature signals, that gives you a complex sampling rate of about 12 MSamples/second, and a theoretical bandwidth of 12 MHz. Usable bandwidth will be more like 10 MHz.
Because of this USB-imposed bandwidth limitation, I chose to use a faster ADC to oversample the input and simplify the analog filtering going into the ADC. I’m expecting to oversample the baseband signal by 4x to 8x. With that amount of oversampling, simple four-pole Butterworth or Bessel filters should be plenty. The FPGA will do sample rate conversion, using CIC or FIR filters.
There’s almost no filtering on the ADC input. I’m planning to attach a separate baseband filter or use an RF band-selection filter to severely band-limit my target signals and avoid unsightly aliasing. Here’s one approach for an 80 MHz sampling rate and a 10 or 12 MHz output rate:
The great thing about oversampling is you don’t have to design your analog filter for the final sample rate’s Nyquist frequency. Instead, you can push that stop-frequency up to the sampling rate minus the final bandwidth. In the example above, it’s 80 MHz minus 6 MHz, or 74 MHz. So my filter can gracefully tail off across more than a decade of frequency (74:6 = 12.3x). Of course, with oversampling, I’ve made a lot more work for myself in the digital domain. But FPGA CIC and FIR filter implementations are plentiful and well-understood, so I’m not too worried…
The board should be back from Laen in a couple of weeks. I can’t wait to solder it up and see what happens!