I’m working with FPGAs and CPLDs a lot lately. Usually, the development tools require vendor-specific programming cables. I don’t have the vendor programming cables, but I do have an FTDI FT2232H integrated onto my board that I can wire to the Lattice XP2 FPGA as a JTAG interface. Combined with urJTAG, I was able to program my board’s FPGA. There were several hurdles:
- urJTAG requires a BSDL file for programming. I was able to download a BSDL file for my FPGA from the Lattice Web site.
- urJTAG can only program using SVF files, at the moment. I tried the new STAPL support, but it crashes. It might be something wrong with my build environment.
- Lattice Diamond does not output SVF files. I needed to download the separate ispVM System program.
- ispVM System outputs an SVF file that urJTAG doesn’t like. Use the “Rev D” SVF output option.
- SVF programming of the XP2 flash is extremely slow. I’m not sure, but I think the SVF has a delay that accounts for time required to erase the flash. I eventually realized that, for development, I could load a bitstream into the FPGA’s SRAM far faster.
Here’s what a programming session looks like:
jtag> cable ft2232 vid=0xcafe pid=0xbabe interface=1 driver=ftdi-mpsse
jtag> bsdl path /Users/jboone/src/bsdl
IR length: 8
Chain length: 1
Device Id: 00000001001010011001000001000011 (0x01299043)
jtag> svf <filename>.svf progress stop
detail: Parsing 23450/23458 ( 99%)detail:
detail: Scanned device output matched expected TDO values.
This technique should work with the Bus Blaster, too, since it’s based on the FT2232H.